Formal Analysis of Steady State Error in Feedback Control Systems

The meticulousness of safety critical control system design has always been of vital significance as even a trifling glitch in the design analysis may result in grievous penalties, even in the loss of human life. To ensure the correctness of the system, traditionally it based on paper and pencil proofs. With the beginning of the modern age, simulations and computer algebra systems were employed to ensure the correctness of design. However, the said techniques compromise the accuracy of the analysis and thus are not a viable option for the analysis of safety critical systems. Over the years Formal Verification has emerged as one of the most viable option for the verification of hardware and software systems. It combines the strong paper and pencil mathematics along with modern computer aided tool to ensure correctness. Since the new formal model must satisfy the existing mathematical reasoning, therefore the chance to catch critical design errors increases which are often ignored otherwise. This thesis makes use of formal methods to establish a higherorder logic based framework to reason about the correctness of safety critical control systems. In particular, we first provide a generic platform to express a wide variety of control systems in terms of their formal model. We identified the least basic blocks which can be arranged in various topologies to express a wide range of systems. We then provide theorems which can be used to reason